1. Field of the Invention
The present invention relates to an apparatus and a method for increasing semiconductor device density. In particular, the present invention relates to a vertical multi-chip device using combined flip chip and wire bond assembly techniques to achieve densely packaged semiconductor devices, and a method for producing such devices.
2. State of the Art
Definitions: The following terms and acronyms will be used throughout the application and are defined as follows:
BGAxe2x80x94Ball Grid Array: An array of minute solder balls disposed on an attachment surface of a semiconductor die wherein the solder balls are refluxed for simultaneous attachment and electrical communication of the semiconductor die to a printed circuit board.
COBxe2x80x94Chip On Board: The techniques used to attach semiconductor dice to a printed circuit board, including flip chip attachment, wirebonding, and tape automated bonding (xe2x80x9cTABxe2x80x9d).
Flip Chip: A chip or die that has a pattern or array of terminations spaced around the active surface of the die for face down mounting of the die to a substrate.
Flip Chip Attachment: A method of attaching a semiconductor die to a substrate in which the die is inverted so that the connecting conductor pads on the face of the device are set on mirror-image pads on the substrate (such as a printed circuit board), and bonded by solder reflux or a conductive polymer curing.
Glob Top: A glob of encapsulant material (usually epoxy or silicone or a combination thereof) surrounding a semiconductor die in a COB assembly.
PGAxe2x80x94Pin Grid Array: An array of small pins extending substantially perpendicularly from the major plane of a semiconductor die, wherein the pins conform to a specific arrangement on a printed circuit board or other substrate for attachment thereto.
SLICCxe2x80x94Slightly Larger than Integrated Circuit Carrier: An array of minute solder balls disposed on an attachment surface of a semiconductor die similar to a BGA, but having a smaller solder ball pitch and diameter than a BGA.
State-of-the-art COB technology generally consists of three semiconductor die to printed circuit board conductive attachment techniques: flip chip attachment, wirebonding, and TAB.
Flip chip attachment consists of attaching a semiconductor die, generally having a BGA, an SLICC or a PGA, to a printed circuit board. With the BGA or SLICC, the solder or other conductive ball arrangement on the semiconductor die must be a mirrorimage of the connecting bond pads on the printed circuit board such that precise connection is made. The semiconductor die is bonded to the printed circuit board by refluxing the solder balls. With the PGA, the pin arrangement of the semiconductor die must be a mirror-image of the pin recesses on the printed circuit board. After insertion, the semiconductor die is generally bonded by soldering the pins into place. An under-fill encapsulant is generally disposed between the semiconductor die and the printed circuit board for environmental protection and to enhance the attachment of the die to the board. A variation of the pin-in-recess PGA is a J-lead PGA, wherein the loops of the J""s are soldered to pads on the surface of the circuit board. Nonetheless, the lead and pad locations must coincide, as with the other referenced flip-chip techniques.
Wirebonding and TAB attachment generally begins with attaching a semiconductor die to the surface of a printed circuit board with an appropriate adhesive, such as an epoxy. In wirebonding, a plurality of bond wires are attached, one at a time, to each bond pad on the semiconductor die and extend to a corresponding lead or trace end on the printed circuit board. The bond wires are generally attached through one of three industry-standard wirebonding techniques: ultrasonic bondingxe2x80x94using a combination of pressure and ultrasonic vibration bursts to form a metallurgical cold weld; thermocompression bondingxe2x80x94using a combination of pressure and elevated temperature to form a weld; and thermosonic bondingxe2x80x94using a combination of pressure, elevated temperature, and ultrasonic vibration bursts. The die may be oriented either face up or face down (with its active surface and bond pads either up or down with respect to the circuit board) for wire bonding, although face up orientation is more common. With TAB, ends of metal leads carried on an insulating tape such as a polyimide are respectively attached to the bond pads on the semiconductor die and to the lead or trace ends on the printed circuit board. An encapsulant is generally used to cover the bond wires and metal tape leads to prevent contamination.
Higher performance, lower cost, increased miniaturization of components, and greater packaging density of integrated circuits are ongoing goals of the computer industry. Greater integrated circuit density is primarily limited by the space or xe2x80x9creal estatexe2x80x9d available for mounting die on a substrate such as a printed circuit board. Conventional lead frame design inherently limits package density for a given die size because the die-attach paddle of the lead frame must be larger than the die to which it is bonded. The larger the die, the less space that remains around the periphery of the diebonding pad for wire bonding. Furthermore, the wire bonding pads on the standard lead frame provide anchorage for the leads when the leads and the die are encapsulated in plastic. Therefore, as the die size is increased in relation to a given package size, there is a corresponding reduction in the space along the sides of the package for the encapsulating plastic which joins the top and bottom of the plastic body at the mold part line and anchors the leads. Thus, as the leads and encapsulant are subjected to the normal stresses of subsequent forming and assembly operations, the encapsulating plastic may crack, compromising package integrity and substantially increasing the probability of premature device failure.
A so-called xe2x80x9cleads over chipxe2x80x9d (LOC) arrangement eliminates the die-attach paddle of the lead frame and supports the die by its active surface from the inner lead ends of the lead frame. This permits a wider variety of bond pad patterns on the die, extends the leads-to-encapsulant bond area and, with appropriate design parameters, can reduce the size of the packaged device for a given die size.
One method of increasing integrated circuit density is to stack die vertically. U.S. Pat. No. 5,012,323 (xe2x80x9cthe ""323 patentxe2x80x9d) issued Apr. 30, 1991 to Farnworth teaches combining a pair of die mounted on opposing sides of a lead frame. An upper, smaller die is back-bonded to the upper surface of the leads of the lead frame via a first adhesively coated, insulated film layer. A lower, larger die is face-bonded to the lower lead frame die-bonding region via a second, adhesively coated, insulative film layer. The wire-bonding pads on both upper die and lower die are interconnected with the ends of their associated lead extensions with gold or aluminum bond wires. The lower die must be slightly larger than the upper die in order for the die pads are to be accessible from above through a bonding window in the lead frame such that gold wire connections can be made to the lead extensions. This arrangement has a major disadvantage from a production standpoint, since the different size dice require that different equipment produce the different die or that the same equipment be switched over in different production runs to produce the different die.
U.S. Pat. No. 5,291,061 issued Mar. 1, 1994 to Ball teaches a multiple stacked die device containing up to four stacked dice supported on a die-attach paddle of a lead frame, the assembly not exceeding the height of current single die packages, and wherein the bond pads of each die are wirebonded to lead fingers. The low profile of the device is achieved by close-tolerance stacking which is made possible by a low-loop-profile wirebonding operation and thin adhesive layers between the stacked dice.
U.S. Pat. No. 5,323,060 issued Jun. 21, 1994 to Fogal et al. teaches a multichip module that contains stacked die devices, the terminals or bond pads of which are wirebonded to a substrate or to adjacent die devices.
U.S. Pat. No. 5,422,435 to Takiar et al. teaches stacked dice having wire bonds extending to each other and to the leads of a carrier member such as a lead frame.
U.S. Pat. No. 5,399,898 issued May 21, 1995 to Rostoker (xe2x80x9cRostokerxe2x80x9d) teaches multichip, multitier semiconductor arrangements based on single and double-sided flip-chips. Rostoker discloses bridging a die over and between two adjacent dice. However, Rostoker intuitively requires the die and bond pad bump patterns be specifically designed to achieve proper electrical communication between the bridged die.
Therefore, it would be advantageous to develop a technique and assembly for increasing integrated circuit density using non-customized die configurations in combination with commercially-available, widely-practiced semiconductor device fabrication techniques.
The present invention relates to an apparatus and a method for increasing integrated circuit density. The apparatus comprises at least an upper die and an opposing lower die which is connected to a substrate (the term xe2x80x9csubstratexe2x80x9d will be used for purposes of this application to mean either substrate carrying traces or other conductors, or a leadframe). The lower die is preferably a flip chip having, for example, C4 solder bump connections, conductive polymer bumps, pin connections, or surface mount J-lead connections extending substantially perpendicularly from the face surface of the lower die. The substrate is configured with a specific lead end or trace end pattern compatible with the specific pin out or bump connections on the flip-chip.
A layer of adhesive, in some instances an electrically insulative adhesive as required or desired to electrically isolate adjacent dice, is applied over the back side of the lower die. The back side of the upper die is placed on the adhesive, thereby attaching the upper die to the lower die, and the adhesive is cured. Preferably, the face or active side of the upper die includes a plurality of bond pads. Bond wires of gold, aluminum or other suitable materials as known in the art are attached between the upper die bond pads and a corresponding trace end or lead end on the substrate.
It is, of course, understood that the electrical connection between the upper die and the substrate can be achieved with TAB technology, wherein metal tape leads are attached between the bond pads on the upper die and the leads on the substrate. However, such an approach obviously requires undesirable pre-planning of bond pad and trace end locations for fabrication of the TAB tape.
An encapsulant is generally used to cover the bond wires and metal tape leads to prevent contamination. Preferably, the exposed circuitry of the die stack is sealed from contamination by an underflow compound for the (lower) flip chip and a glob top over the entire assembly after wire bonding.
Such an arrangement increases semiconductor device density using noncustomized die and bond pad patterns, and commercially-practiced conductor attachment techniques.
If the upper die is smaller than the lower die, one or more small, additional, discrete components such as resistors, capacitors, or the like can be attached to the back side of the lower die via a portion of the adhesive not covered by the upper die. Bond wires can be attached between the upper die and the discrete component(s), if desired, as well as between the component(s) and the substrate. This arrangement frees up real estate on the substrate that would normally be taken up by the component, thereby further increasing potential integrated circuit density.
A multitude of die arrangements can be conceived using the technique of the present invention. For example, an additional (third) die can be added to the above arrangement. An adhesive is added to the active surface or face of the upper die (without covering the bond pads) and the back side of the additional die is applied to the adhesive, thereby attaching the additional die to the upper die. Preferably, the face side of the additional die has a plurality of bond pads. Bond wires are attached between the additional die bond pads and corresponding trace or lead ends on the substrate.
Of course, the bond wires can be attached from the additional (third) die to a component attached to the adhesive not covered by the upper die, and/or, if the additional die is smaller than the upper die, a component can be attached to the adhesive on the face of the upper die and bond wires attached thereto.
As another example, a pair of lower dice can be connected to the substrate with the upper die bridged between the lower die. The upper die is adhered to both lower dice with the layers of adhesive applied over both lower dice back sides. Bond wires are attached in the manner discussed above. Furthermore, still more additional dice can be stacked or discrete components attached to the assembly in the manner discussed above.